The present invention relates to a sample and hold circuit having reduced offset. More specifically the present invention relates to a sample and hold stage with a low leakage switch.
Sample and hold stages are used in a wide variety of circuitry and applications. A sample and hold stage typically includes a sampling capacitor and a plurality of switches. An input switch connects one side of the sampling capacitor to an input voltage. After this sampling phase the input switch opens and the charge on the sampling capacitor is frozen. The voltage level on the sampling capacitor is maintained during the hold phase while the input switch is open. Typically, an amplifier, e.g. configured as a voltage follower, is coupled to the sampling capacitor for buffering the sampled voltage level on the capacitor.
However, if the input switch is implemented as a MOS transistor, opening of the transistor has the undesired effect that leakage currents from the transistor add charge on the sampling capacitor. This situation is illustrated in FIG. 1. The operational amplifier AMP is configured as a non-inverting amplifier, with an amplification factor A. The input switch S1 consists of a single NMOS transistor NM1. Transistor NM1 is coupled between the input node Vin and the sampling capacitor C, which is also coupled to the non-inverting (positive) input of the amplifier having a voltage level V1. The leakage current includes a first component Im relating to a subthreshold current of the MOS transistor NM1. A second component of the leakage current is the leakage current Id relating to the bulk-source diode of the MOS transistor NM1.
FIG. 2 shows a known principle to avoid the component Im of the leakage current due to the subthreshold current of the transistor NM1. A switch S5 is coupled between the input node Vin and the first switch S1. The intermediate input node V4 between the first switch S1 and switch S5 is also coupled to a switch S4. When the first switch S1 and the switch S5 open, i.e. during the hold phase, the switch S4 is closed. The intermediate input node V4 is then coupled to a node V3. Node V3 has substantially the same voltage level as V1. Since no voltage drop across S1 exists, the leakage current component Im is reduced to a small residue that is due to the input offset voltage of the amplifier AMP. The following Table 1 shows the positions of the switches S1, S5, S4 during the sample and during the hold phase:
TABLE 1S1S5S4SampleCCOHoldOOC
C stands for close and O stands for open, wherein close means that the switch provides a connection and open means that the switch disconnects.
The circuit shown in FIG. 2 only reduces the first component Im of the leakage current. The second component Id is unaffected. The conventional solution for reducing Id involves minimizing the ratio between the source area of NM1 and the sampling capacitor C to make it as small as possible. However, there are many constraints which contravene this approach, as for example the switching or settling speed of the circuit or the maximum allowable area consumed by the capacitor C.